1. Field of the Invention
The present invention relates to semiconductor structures having a memory element, which is protected from interferences by an integrated shield.
2. Description of the Related Art
With an increasing packing density of electronic elements, such as transistors, which are integrated on a chip, the significance of efficient protective measures against electromagnetical or electrostatic interferences increases. If memory elements, for example, are constructed with the help of transistors, the stored amount of charge might no longer be detected correctly, if, for example either the amount of the stored amount of charge or its sign have changed significantly due to an electrical interference field. This is particularly problematic, if EEPROMs are used for permanent storage of data (EEPROM=electrically erasable programmable read only memory), since an EEPROM cell is particularly susceptible against external interference fields.
Principally, an EEPROM cell is constructed similar to a MOS transistor (MOS=metal oxide semiconductor). In FIG. 1, a schematic diagram of an EEPROM cell (100) is illustrated, as it is known from the prior art. First, the EEPROM cell is characterized by a control terminal 102, a floating gate electrode 104, a source terminal 106, a drain terminal 108 as well as a substrate or bulk terminal 110. A coupling capacity 112 is effective between the control terminal 102 and the floating gate 104, and the known MOS capacity 114 is effective between the floating gate 104 and the bulk terminal 110.
In FIG. 2, the setup of an EEPROM cell is illustrated, as it is known from the prior art. In a substrate (bulk) 116, such a p-substrate (p bulk), an n+ source area 118 and an n+ drain area 120 are formed. A channel area 122 is formed between the n+ source area 118 and the n+ drain area 120. A thin oxide layer 126 is formed on a surface 124 of the substrate 116, where the floating gate 104 is formed. An oxide layer 128 is formed on the floating gate, where again a control electrode 130 (control gate=CG) is formed, which is connected to the control terminal 102. The n+ source area 118 is connected to the source terminal 106, and the n+ drain area 120 is connected to the drain terminal 108. The substrate 116 is connected to the bulk terminal 110 at the surface 132 opposite to the surface 124. The coupling capacity 112 is formed by the control electrode 130, the floating gate 104 and the oxide layer 128 lying between them. The MOS capacity 113 is formed by the floating gate 104, the thin oxide layer 126 and the substrate 116. In the setup of the EEPROM illustrated in FIG. 2, this is an n-type EEPROM. The EEPROM cell can also be formed as p-type EEPROM. In this case, the substrate would be an n-substrate or an n-well would be formed in the p-substrate 116, where a p+ source area and a p+ drain area would be formed. In this case, the n-substrate and the n-well, respectively, would be the bulk of the p-type EEPROM.
The difference between the EEPROM cell and a MOS transistor is that two electrodes are provided for controlling in the EEPROM cell, the floating gate 104 (FG) and the control electrode 130 (CG). The floating gate 104 is directly opposite to the MOS channel area 122, which is formed between the source area 118 and the drain area 120, only separated by the thin oxide 126, and is not connected to further parts of the circuit in an electrically conductive way, which is why it is electrically “floating”. By the other, mostly thicker, oxide 128, the control electrode 130 is separated from the floating gate 104 and connected to the control terminal 102. Thus, seen from the outside, the EEPROM cell is similar to a MOS transistor with source, drain, bulk and gate terminals. Particularly, in the EEPROM cell, an effective threshold voltage, Uth,eff can be defined, like in the MOS transistor. In an n-type EEPROM, which corresponds to an NMOS, the control electrode 130 has to be raised above the source potential at least by Uth,eff, so that the channel formed between the drain area 128 and the source area 126 becomes conductive.
By different physical mechanisms, such as by Fowler Nordheim tunneling (FN) or Hot Carrier Injection (HCI), an excess or a deficiency of net charge can be generated at the floating gate 104. Therefore, a comparatively high voltage of a positive or negative polarity has to be applied between control terminal 102 and the bulk terminal 110, whereby the respectively smallest information unit (bit) is stored in the form of this net charge or not, whereby, for example, a logical “1” or a logical “0” can be realized. It can be seen that after this programming the changed net charge at the floating gate 104 leads to a change of the effective threshold voltage. If the floating gate 104 is not charged, the respective effective threshold voltage is called UV level. This designation stems from the fact that an uncharged state can be achieved by irradiating the floating gate of the EEPROM cell with UV light for several minutes.
If a high positive potential is applied to the control terminal 102 due to the programming, a negative net charge (electron excess) occurs at the floating gate 104, as long as the coupling capacity 112 is larger than the MOS capacity 114, which is always assumed in the following. The effective threshold voltage will therefore be shifted to positive values; it is therefore larger than the UV level. If the control terminal 102 is provided with a strongly negative potential against the substrate 116 in the programming, a positive net charge (electron deficiency) is obtained at the floating gate 104, and the threshold voltage becomes smaller than the UV level.
In the following, the programming is explained with an example of the Fowler Nordheim Tunnel mechanism, as it is known from the prior art.
If a positive voltage ramp is applied at the control terminal 102, first, at small voltages, a separation of the voltage into two fractional voltages occurs, namely a voltage at the coupling capacity 112 (coupling capacitor), and a second voltage between the floating gate 104 and the MOS channel and substrate 116, respectively, which drops at the MOS capacity 114. According to the common rules for capacitive voltage dividers, the ratio of the coupling capacity 112 to the MOS capacity 114 is inverse proportional to a ratio of the fractional voltages dropping at these two capacities. For that reason, an effort is made to make the coupling capacity larger than the MOS capacity 114, so that a portion of the total applied voltage as high as possible drops at the thin oxide 126 of the MOS capacity 114, and affects the Fowler Nordheim tunneling there. This is achieved constructively by making the lateral dimensions of the thin oxide 126 defined by a layout smaller than those of the oxide 126 between the control electrode 130 and the floating 104. If, therefore, the voltage applied to the control terminal 102 is ramped up, the two fractional voltages rise as well, until finally the larger fractional voltage—namely the one at the thin oxide 126—achieves a field strength of, for example, about 8 MV/cm to about 9 MV/cm. Then, the Fowler Nordheim tunneling begins, i.e. a small stream flows above the thin oxide 126 from the floating gate 104 to the MOS channel and the substrate 116, respectively. The rise time of the voltage ramp should thereby be so small that those processes run more or less statically. Thus, a small Fowler Nordheim tunnel current is enough to load the coupling capacity 112 sufficiently fast, so that the potential at the floating gate 104 remains, for example, at a value of Um=8 . . . 9 MV/cm*D. Thereby, D indicates a thickness of the thin oxide 126.
If a maximum programming voltage is finally Up, a difference between Up and Um is stored at the coupling capacity 112. This can be expressed as follows:|UP|−Um=|Uc|=|Q(FG)|*Cc 
Thereby, Q(FG) is the charge stored at the floating gate 104, and Cc is the value of the coupling capacity 112. In the above expression, for simplicity reasons, the sign was omitted, which reflects in the amount-like version of the charge stored at the floating gate 104. The normal rise times of the voltage ramps are between 100 μs . . . 10 ms.
If, however, the rise time of the programming pulse is shorter, the small Fowler Nordheim tunnel stream is no longer sufficient to load the coupling capacity 112 sufficiently fast, so that the voltage at the thin oxide 126 rises above Um, and damages the thin oxide 126 more than absolutely necessary. This pre-damage is shown by the fact that the floating gate 104 looses the charge over time, and it comes to a data loss, which, of course, has to be avoided.
A bit error occurs, if, for example, high voltages at the thin oxide 126 (also referred to as gate oxide) of the MOS capacity 114 change a charge state of the floating gate 104, whereby, for example, the sign of the stored charge changes. Often, however, it is already sufficient for a bit error when merely the amount of the charge stored at the floating gate is reduced sufficiently, without changing the sign. The reason therefore is that it is difficult in practice to apply the exact UV level as an ideal discrimination value between the positive and the negative charge at the floating gate 104 at the control electrode 102. On the one hand, there are the discrimination value varies with temperature, on the other hand, the strong variations from batch to batch, disc to disc, chip to chip and even within a chip in dependency of a position of the memory element (memory cell) in the chip, which are common in the memory in the semiconductor technology.
In practice, it can happen that an integrated circuit (IC) is subject to a high electrical field. This is particularly the case in electrically “rough” environment, such as in the use in an automobile. Therefore, it is extremely important in security relevant applications that the IC functions properly despite an adverse electrical environment, particularly that it is not damaged thereby. For a function of the IC, often those data are relevant which are stored in the EEPROM cell. As an example, imagine an integrated magnetic-field sensor, which is to detect a blocking of a wheel in an ABS system (ABS=anti blocking system), and whose calibration data are stored on chip in an EEPROM. If these calibration data are, for example, lost by an electrical field pulse, the blocking of a wheel is continuously not detected, or in another extreme case, never detected. The consequences of such damage can be dramatic.
Particularly high electric fields can occur in ESD events (ESD=electrostatic discharge). Here, again, that case is to be seen as worst case, where the discharge takes place above a housing to the IC. Thereby, a tip of an ESD pistol is held directly to a surface of the IC, and, for example, charged to several kilovolt against ground. If the IC is applied to ground at the same time, an ESD flash can discharge above that part of a compound of the housing directly under the tip of the ESD pistol. If an EEPROM cell is within this area on the surface of IC, it can be damaged thereby.
In the following, the orders of the influence of an ESD event to an EEPROM cell are estimated.
As a model, the tip of the ESD pistol and the ESD cell is replaced by a small ball, since the capacity of a ball spark gap can be calculated analytically without too much effort as follows:
  C  =                    πɛ        0            ⁡              (                              2            ⁢            R                    +          g                )              ⁢                  ∑                  p          =          1                ∞            ⁢                          ⁢              1                  sinh          ⁡                      (                          par              ⁢                                                          ⁢                              sinh                ⁡                                  (                                      1                    +                                          g                                              2                        ⁢                        R                                                                              )                                                      )                              
Thereby, R is the radius of the ba s and g the distance of their facing surfaces, ε0 is the electrical field constant. For thin housings, particularly with magnetic-field sensors, g=0.15 mm has to be assumed. arsinh ( . . . ) is the arcus sinus hyperbolic function and p is the sum index. Depending on the radius of the ball R, the following stray capacitances result from the above expression:
RC100nm5.6aF1μm56aF10μm0.59fF100μm7.4fF1mm8.7fF
In practice, naturally, the EEPROM cell is very small (smaller than 1 μm), the tip of an ESD diode or the fingertip of a human being is comparatively large (larger than 1 mm), so that the above model of the ball spark gap is not very well suitable for an exact calculation of the influence of the ESD event on an EEPROM cell. Still, this model can be used for a best-case estimation. The stray capacity between the fingertip and the EEPROM cell is definitely larger than the one between two balls with 1 μm radius, since the fingertip is significantly larger than 1 μm and according to the above table, the capacity rises also with increasing radius. Even this small stray capacity of 56 aF between fingertip and floating gate 104 effects that at an assumed coupling capacity 111 Cc=20 fF already the 20/0.056=357-th part of the ESD voltage is applied to the thin oxide. Thus, at a value of the ESD voltage of, for example, 4.6 kV, 13 V are applied to the thin oxide. This is already sufficient for the FN tunneling for a thickness of 12 nm assumed in this example.
Due to the above-described problem it is thus necessary to shield the floating gate 104 appropriately. This can, for example, be realized by covering the floating gate 104 fully with the control electrode 130, so that the control electrode 130 electrically shields the floating gate 104. This shield effect can be insufficient, when the control electrode 130 is not low-resistively connected to the substrate 116 of the EEPROM cell. Assumed that a person who is electrostatically charged touches the IC. The stray capacity between the fingertip of the person and the control electrode 130 raises-the potential of the control electrode 130, when the control electrode 130 is not brought to a defined potential by other circuit parts. This case occurs particularly when the IC is not supplied with a voltage, because then the inner nodes of an MOS circuit have a high impedance, since no sufficient potentials are present at the gates of the belonging MOS transistors in order to switch those to being conductive. The coupling capacity 112 formed by the floating gate 104, the oxide layer 128 and the control electrode 130 influences then subsequently the potential of the floating gate 104, so that its charge state might change.